Miniaturization has been advance to realize LSI high performance, and a gate length has been reduced. Since the gate length has been reduced, a diffusion depth of a source/drain region must be decreased. For example, in case of a device (a transistor) having a gate length of approximately 30 nm, a source/drain portion has a diffusion length of approximately 15 nm, and very shallow diffusion is required.
In conventional examples, to form such a diffusion layer, ion implantation is used, and a method for implanting, e.g., B+ or BF2++ at very low acceleration of 0.2 to 0.5 keV is adopted. However, atoms which have undergone the ion implantation cannot reduce a resistance thereof as they are. Further, in a region where the ion implantation has been carried out, point defects such as interstitial silicon or atomic vacancies are produced in a silicon substrate.
Thus, after the ion implantation, annealing is performed to activate the atoms (reduce the resistance) and recover the defects, but the ion-implanted atoms diffuse and an impurity distribution spreads due to this annealing. Furthermore, there is also known a phenomenon that impurity diffusion is accelerated by not only the annealing but also the point defects produced due to the ion implantation.
To enable formation of a shallow p-n junction of 10 nm or less in a transverse direction immediately below an ion implantation mask at a depth of 15 nm or less even though the spread of diffusion is taken into consideration, an annealing method of applying high energy in a very short time has been examined and adopted (see, e.g., Patent Literature 1).
As this method for annealing, there is, e.g., annealing which uses a flash lamp having a rare gas such as xenon enclosed therein. This lamp is a method for applying high energy of tens of J/cm2 or more as pulse light of 0.1 to 100 milliseconds. Thus, activation can be carried out without substantially changing the impurity distribution formed by the ion implantation.
However, since this high energy is used, it can be considered that thermal stress in the silicon substrate increases and damage such as cracks or slips of the silicon substrate are caused, and an examination for this has been actually conducted.
For example, Patent Literature 2 has a description in which, to form a shallow impurity diffusion region without causing damage in a semiconductor substrate, materials having a material which serves as an acceptor or a donor to the semiconductor substrate and a material which does not serve as the acceptor or the donor to the semiconductor substrate are implanted into the semiconductor substrate.
It is known that crystal defects such as point defects are recovered by a heat treatment as described above. However, particulars of this recovery process are not known, and hence performing precise defect control is difficult in conventional methods.